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Abstract
Bio-inspired neuromorphic computing systems built with emerging devices such as memristors have extensively reported experimental demonstrations at the network-level and attracted great interest as a promising candidate to overcome the von-Neumann bottleneck for the future computing applications. As a hardware system that offers co-location of memory and data processing, memristor-based networks enable efficient computing platform through minimal data transfer and higher parallelism. On the other hand, active utilization of dynamic processes during resistive switching in memristor realizes more faithful emulation of biological network behaviours with natural fashion and offers potential to process dynamic tempol inputs efficiently.
In this seminar, we focus on what kind of tasks are possible with memristor-based neural network. Firstly, K-means clustering, unsupervised algorithm, is experimentally demonstrated using proposed network structure and learning rules, which extends data processing of memristor network to a cheap unlabelled dataset. Secondly, we further widen capability of memristor network from ‘soft’-computing to ‘hard’-computing using memristor-based partial differential equation (PDE) solver. The expensive computing task requiring extremely high precision (up to 64-bits) is successfully demonstrated in memristor network through precision extension techniques and this work paves the way for the development of more general-purpose, memristor-based computing systems. Lastly, faithful emulation of biology behaviours is demonstrated in newly proposed memristor model, 2nd-order memristor, and the network presents ability of temporal data processing only relying on device internal dynamics.
We anticipate a fully integrated computing system based on arrays of memristor crossbars monolithically integrated on complementary metal-oxide-semiconductor supporting circuitry can offer a scalable computing system with very high processing speeds and power efficiency, owing to its ability to natively compute information in-memory and to its high level of parallelism.
 
Short Bio
YeonJoo Jeong received the B.S. degree in the College of Engineering Sciences from University of Tsukuba, Tsukuba, Japan, in 2007, and the M.S. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2009. After that, he worked at NAND Flash division of SK Hynix to replace his military duty. From 2014, he is currently pursuing the Ph.D. degree at the EECS department of the University of Michigan, Ann Arbor, MI, USA and his research interests include memristor devices and its network applications, with an emphasis on demonstration of algorithms using memristor crossbar array. He is a recipient of Korea-Japan joint government scholarship program from 2002 to 2007 and IEEE EDS Japan chapter student award 2008.