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ISSL’s paper accepted to HPCA 2022

 

A research paper entitled “DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX” has been accepted for publication in HPCA’22. The paper is co-authored by Sowoong Kim, Myeonggyun Han and Prof. Woongki Baek at Intelligent System Software Lab. (ISSL), CSE, UNIST.

In this work, we discover the vulnerability caused by the undocumented interactions between the coherence directories and Intel TSX transactions in latest Intel CPUs with non-inclusive cache hierarchies. Guided by the observation, we propose a high-precision and timer-free directory attack called DPrime+DAbort in non-inclusive cache hierarchies using Intel TSX, which nullifies the countermeasure based on non-inclusive cache hierarchies and overcomes the countermeasure based on coarse-grained and/or noisy timers. We demonstrate the practicality of the DPrime+DAbort attack in that it can be used to attack cryptographic and genome-sequencing applications.

HPCA (International Conference on High-Performance Computer Architecture) is one of the top-tier conferences in the field of computer systems.