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Two papers are selected for presentation at ISSCC 2019

Activities November 13, 2018

The first authors: Juyeop Kim, Heein Yoon, Younghyun Lim, and Seyeon Yoo in the Ph.D. program of ECE (From the left side)

 

Two ICSL (Prof. Jaehyouk Choi)’s papers have been accepted for presentation at IEEE ISSCC (International Solid-State Circuits Conference) in San Francisco in February 2019.

 

ISSCC is the single most prestigious conference in the field of semiconductor circuits and systems and also called “Semiconductor Olympic”. Since the first event in 1954, every year more than 3,000 researchers from industry and academia all over the world participate to present and exchange state-of-the-art technologies and research outcomes. The next year’s ISSCC is the 66th and has a theme “Envisioning the Future”.

 

In this year, UNIST made a remarkable achievement by making two papers selected, and it is ranked at the 3rd place with Seoul Univ., Yonsei Univ., and SK Hynix, among the institutions of Korea, following Samsung Electronics and KAIST, which tied for 1st place.

 

The first authors of the first selected paper are Juyeop Kim, Heein Yoon and Younghyun Lim (Equally-Credited Authors, ECAs). In their research, they present transceiver-IC technologies for future 5G mobile communications, which are expected to be the fundamental technologies for the successful launch of 5G in the global market.

 

In the other paper, Seyeon presents a new, low-reference spur, low-jitter, ring-VCO-based clock generator to overcome major drawbacks of conventional injection-locked clock multipliers. The circuit proposed by Seyeon is expected to make the manufacturing cost of semiconductor chips greatly reduced.

 

L1-level conference: 2019 IEEE International Solid-State Circuit Conference (ISSCC), February, 2019

 

1. Authors: Juyeop Kim, Heein Yoon, Youngyhun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, and Jaehyouk Choi

 

Title: A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

 

2. Authors: Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, and Jaehyouk Choi

 

Title: A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator