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ECE Colloquium: Myoungsoo Jung(Yonsei University) “Memory Hierarchy Revision by Taking into Account Flash and New Memories”

May 16, 2018 / 16:00 ~ 17:15

Speaker : Myoungsoo Jung

 

Abstract

Data is exploding and generated more in just the last year than in the entire previous history of industry. The data volumes are growing faster than ever before and expected to keep increasing to Yottabyte for the next decade. While this big data explosion can open to a series of new semiconductor business opportunities, memory scaling is unfortunately limited due to a low storage core reliability and significant core-to-core interference. In this talk, we will mainly discuss several innovative concepts to bridge the gap between storage demand and supply at the data age 2025. Specifically, this talk advocates radically different system-level and architecture-level approaches that i) revise traditional memory hierarchy, ii) process data from creation, iii) shorten the existing datapath and iv) integrate new memory and flash into hardware coprocessors. For each approach, I will touch one or two on-going research items that span from datacenter to enterprise edge to connected device systems.

 

Short Bio

Dr. Myoungsoo Jung is Assistant Professor at Yonsei University. Dr. Jung earned his Ph.D. in Computer Science at Pennsylvania State University and his M.S. in Computer Science from Georgia Institute of Technology, and an M.S. in Embedded System from Korea University in Seoul. Dr. Jung has many years of industry experience, several industrial U.S. patents related to multi-channel SSDs, and approximately forty technical papers regarding SSD flash firmware and kernel-level file systems. His research has been nominated as best paper from the Institute of Electrical and Electronics Engineers/Association for Computing Machinery (IEEE/ACM) Internal Conference for High Performance Computing, Networking, Storage and Analysis 2013 (SC’13). He received core grant awards from National Science Foundation (NSF) and Department of Energy (DOE), respectively, and the Lawrence Berkeley National Laboratory Award (LBNL) of Excellence. His current research interests include coprocessor architecture (e.g., MIC/GPU), FPGA-based accelerators, advanced computer architecture, and operating systems on emerging non-volatile memory and solid state drive technologies.

Venue

104 E204